With a progress in the fineness of a manufacturing process, the distance between wiring lines of a semiconductor integrated circuit (LSI) has been rapidly decreased. Therefore, it is expected that the incidence of a bridge fault occurring in the LSI will be increased. The ‘bridge fault’ occurs between adjacent wiring lines (hereinafter, referred to as ‘a pair of wiring lines’) due to a foreign material (dust) laid thereon, which causes a short circuit between the wiring lines.
In the related art, an IDDQ test easy to realize has been put to practical use as a bridge fault test for detecting a bridge fault. When a signal having a level of ‘1’ is propagated through one of a pair of wiring lines having a bridge fault and a signal having a level of ‘0’ is propagated through the other line, the IDDQ tester detects a DC current (abnormal IDDQ) value flowing in an LSI, thereby detecting the bridge fault. However, with a progress in the fineness of a manufacturing process, the IDDQ current value considerably increases in a fault-free LSI that operates at high speed, which makes it difficult to apply the IDDQ test.
Therefore, a bridge fault test (hereinafter, referred to as a ‘logic-level bridge fault test’) that inputs a bridge fault test pattern to an LSI and compares the logic values (levels) of output terminals with expected values, instead of measuring an IDDQ current, thereby detecting a bridge fault has become important as a bridge fault test applicable to the LSI. The following bridge fault tests have been proposed as logical bridge fault tests applicable to a large LSI: a simple bridge fault test capable of dealing with a wired-AND or wired-OR bridge fault; and a bridge fault test for accurately modeling a bridge fault by combining circuit information and layout information of an LSI.
When a bridge fault in a pair of wiring lines of an LSI is excited by the logical values of signals passing through the pair of wiring lines which are different from each other, there is a possibility that an erroneous operation will occur in a circuit in the next stage. The ‘propagation of a bridge fault’ means that an erroneous operation caused by an excitation of an bridge fault is propagated through circuits via a circuit in a stage next to a pair of wiring lines having the bridge fault. Since the bridge fault is propagated in the LSI, it is possible to detect the bridge fault at the output terminals of the LSI. It is determined whether a bridge fault is propagated in an LSI and whether the bridge fault may be detected at the output terminal of the LSI on the basis of the following factors: a driving circuit for outputting signals that are propagated through wiring lines having a bridge fault; an input to the driving circuit, the resistance value of bridge fault between the wiring lines; a receiving circuit to which a signal passing through the wiring lines having the bridge fault is input; and a threshold value of an input terminal to which the signal is input. Therefore, it is necessary to appropriately extract the layout information.
In the related art, a bridge fault test is to effectively extract a bridge fault from a large LSI, but it is not well considered to cope effectively with the correspondence between a bridge fault (defect) incidence and the layout information of an LSI. The layout information includes information on the detailed wiring and connection of basic cells, macro cells, wiring lines, and vias for connecting signal lines arranged in different wiring layers in an LSI (hereinafter, referred to as ‘signal line layout information’). For example, the layout information includes detailed layout information of a GDS2 format (real layout level) and layout information after an optical proximity correction (OPC) process. In general, the signal line layout information is combined with information on the shape of the basic cells and the macro cells and the position of terminals and information on a design rule, such as the minimum distance between wiring lines into complete information. From the viewpoint of the estimation of a bridge fault incidence, a tool for accurately extracting a critical area on the basis of data of the layout information of the GDS2 format and the layout information after the OPC process and accurately estimating a yield is already on the market. The ‘critical area’ means an area of an LSI in which wiring lines are closely arranged.
However, in the above-mentioned tool, it is difficult to associate the layout information with a logic net list, which is electrical connection information of an LSI. Therefore, it is difficult to feed back the result of a bridge fault test performed for signals on the logic net list to the layout information and to extract information in order to estimate the quality of a bridge fault test which has a strong correlation to the bridge fault incidence or effectively improve the quality of the test. The ‘test quality’ is generally estimated by the fault coverage. Since the layout information has a large amount of data, there is a problem in that it takes a lot of time to process the layout information.
The signal line layout information can be used to estimate the quality of the test to some extents (for example, see JP-A-2003-107138). That is, an appropriate close distance is set, and a pair of wiring lines that are adjacent to each other at a distance smaller than the close distance are extracted together with the length of the pair of wiring lines. Bridge fault test patterns generated by an automatic test pattern generating tool (program) are applied to the pairs of wiring lines (bridge faults) or a bridge fault test tool to estimate a bridge fault coverage by general test patterns, such as fault simulation, is applied to the pairs of wiring lines. A weighted fault coverage is defined by considering the length of the wiring lines. Actually, as the distance between the pair of wiring lines becomes larger, the bridge fault incidence is rapidly lowered. However, the above-mentioned method does not consider the influence of the above, and does not reflect the layout information to the bridge fault coverage with high accuracy.
As described above, a method of estimating the quality of a bridge fault test considering layout information, that is, a method of accurately calculating a fault coverage of bridge fault test patterns is not disclosed. Therefore, it is difficult to take an effective measure to reduce the incidence of bridge faults using the result of a bridge fault test.